Method of testing a memory

ABSTRACT

A built-in self-diagnostic (BISD) memory device includes a two-dimension memory array provided with a redundant memory rows and columns that can be substituted for various ones in the two-dimension memory array by an external repair facility. A stimulus generator outputs multi-address test sequences to the memory array during a test mode. A response evaluator receives responses from the memory. A fault table stores evaluations of the responses, and communicates them to the external repair facility. A repair register indicates which memory columns have been intermediately scheduled for repair by the response evaluator. Column counters each accumulate the number of memory bit faults detected in a respective memory column. All are disposed in a single integrated circuit semiconductor device.

FIELD OF THE INVENTION

The invention relates to a method for testing a memory array with rowand column redundancy whilst keeping track of row-wise and column-wisemust repair occurrencies, and a memory-based device arranged forpracticing such method.

BACKGROUND OF THE INVENTION

Integrated-circuit memory chips have been growing in size over theyears. Large memories, and in particular DRAMs, have suffered from lowmanufacturing yields. It has become common practice to provide such withspare rows and columns so that after testing these may be used asreplacements. In common manufacturing practice, a 2% redundancy maytriple manufacturing yield. Testing of memory arrays has become arefined art, based on presenting the array with many test stimuli with aprescribed content and in a prescribed sequence, and subsequentlyreading the stored content for comparison with the expected response.The combination of stimulus and expected response is often called thetest pattern.

Of late, processor or other circuitry has been combined with a largeamount of so-called embedded memory. The nature of such other circuitryis not critical to the present invention. For digital processing, thecombination often allows a larger communication bandwidth between memoryand the other circuitry, than between the memory if stand alone and theenvironment, both in terms of the number of wires, and in terms of bitrate per wire. In various aspects, the other circuitry would isolate thememory from the chip's surroundings. The embedded array often has moreI/O bit terminals than the combination has available data pins. Hence,direct access to the array is often unfeasible. Restricting the test toan inexpensive on-chip pass/fail determination, such as through asignature-generating mechanism, would not allow to execute repairoperations.

By itself, the repair poses a so-called NP-Hard Problem. The problem isto determine, for a given set of faulty bit locations in the memory, andfurthermore, for given numbers of spare rows and columns, respectively,the following: whether the memory is repairable, and if so: which faultyrows and/or columns should effectively be repaired

This problem is NP-Hard inasmuch as the time complexity for finding anoptimum solution is exponential in the number of spare rows and in thenumber of spare columns. Fortuitously, in most practical cases it istractable due to the relatively small numbers of repair rows and repaircolumns involved, provided only that the full fault bit map is known.The repair strategy may thus be handled off-chip. However, due to thelarge number of test patterns required, parallel-to-serial conversion ofthe complete response patterns for external verification wouldappreciably slow down the execution of the test. On the other hand,storing the complete fault pattern on-chip would need a second memory ofthe same size as the memory under test, as well as an appreciable andexpensive amount of strategy-determining logic.

Now, a particular aspect of mass testing of memory is not only topinpoint the rows and columns that should be repaired, but also to keeptrack of the amount of repair necessary, and to signal as early aspossible when repair capability is exceeded. Such is difficult, becausea particular bit fault may be part of a row to be replaced, of a columnto be replaced, or of both. During the test, optimum assignment may evenchange due to later detected faults.

Therefore, an improved trade-off should require only moderate extensionsof the on-chip facilities, while at the other hand necessitating onlylittle communication with the external world, whilst still providing alosslessly compressed response pattern. In particular, on-chip storagespace should be kept very low. Also, the loss in manufacturing yieldshould be low.

SUMMARY TO THE INVENTION

In consequence, amongst other things it is an object of the presentinvention to provide a methodology for dynamically assessing theconfiguration of faults already detected to at least in part and foreconomically assigning the faults to repair facilities that are presentaccording to a Must Repair Strategy, and to signal in an early mannerwhen overall repairability cannot be guaranteed any longer.

Now therefore, according to one of its aspects, the invention ischaracterized according to the characterizing part of claim 1. Theinvention also relates to a memory-based device being arranged forimplementing a method as claimed in claim 1. Further advantageousaspects of the invention are recited in dependent Claims.

U.S. Pat. No. 5,337,318 describes a method for tallying both rows andcolumns in a memory array that must be repaired, and in consequence maysignal occurrence of non-repairability. The present invention howeverallows dynamical assignment of certain faults to either a redundantcolumn or to a redundant row for better usage of overall repairfacilities.

BRIEF DESCRIPTION OF THE DRAWING

These and further aspects and advantages of the invention will bediscussed more in detail hereinafter with reference to the disclosure ofpreferred embodiments, and in particular with reference to the appendedFigures that show:

FIG. 1, an integrated circuit architecture embodying the presentinvention;

FIG. 1A, the operation modes of the architecture of FIG. 1;

FIG. 2, a finite state machine organized for executing a 9N March MemoryTest;

FIG. 3, a response evaluator embodiment;

FIG. 4, represents a repair analysis procedure;

FIG. 5 is a block diagram of repair analysis hardware.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

FIG. 1 shows an embodiment of an integrated circuit architectureembodying the present invention. The integrated circuit chip 20 has beenprovided with external pins or bonding pads shown as bundle 36, whichmay comprise digital data, analog signals, control, and power channelsarranged in various sub-bundles of appropriate path width and amplituderanges. Hereinafter, various power and control interconnections areconsidered standard, and will not be disclosed in detail. The sameapplies to the operation of various basic electronic memory features.Now often, a relatively large part of the chip area is used by memory24, that may be based on various technologies, such as DRAM or SRAM.

Block 22 symbolizes in the broadest sense circuitry “other than thememory to be tested” and may comprise processor functionality and/orother memory or non-memory functionality of any applicable nature, suchas single-purpose sequential logic circuitry, analog signal handling,programmable logic array, and other that is generally not based on alayout from uniform cells as memory. The memory under test may bedistributed over a plurality of physically and/or logically distinctarrays, which feature has not been shown for clarity.

Now, in non-test condition of the embodiment, functionality 22 converseswith memory 24, in that blocks 28, 30 are controlled in a transparentmode, so that the signals Chip Enable Bar CEB, Write Enable Bar WEB,Address A, Data In DI, and Data Out DO travel substantially unimpeded.Other embodiments of such signals would be feasible. Block 22communicates unidirectional and/or bi-directional data and controlsignals with external circuits not shown on bundle 36, whichcommunication will generally be governed by the inherent facilitiesprovided in block 22. Furthermore, line 34 communicates fault info, thatmay also run through block 22. In the art, the phrase Built-In-Self-TestBIST means that testing provides Pass/Fail data, the phraseBuilt-In-Self-Diagnosis BISD means that testing points to the actuallyfound faults, whereas Built-In-Self-Repair BISR has also the repairexecuted in-chip, thereby obviating the need for providing externalpointers. The present invention is directed to a BISD scheme.

Now, it is generally expensive to connect all test response linesimmediately to an environment. Therefore, the present invention providesthe adding of a relatively small amount of hardware and control that maybe used to analyze fault patterns upon the finding thereof todynamically at least partially assign such faults to appropriateredundancy available. The strategy is to combine the low-level teststeps with a partial on-chip analysis, the results of which need only asmall amount of storage. Next, the small-size results are outputted forfurther analysis off-chip. The outputting needs little time, and theoff-chip processing can be done in hardware and software that are notsubject to the size restrictions that are imposed on the chip itself.

Now, memory 24 has been provided with BISD functionality located inblock 26 in particular through blocks 28 and 30. Various features of thepresent invention distinguish in advantageous manner. It should be notedthat the present test methodology is directed to mass testing that mustpinpoint all detected faults while needing only little overhead in chiparea as well as in test time. The present invention allows to continuetesting automatically once a particular fault signalization has beenfully analyzed. All available fault data can be automatically signalledto an external device, regardless of the actual internal spacing betweenvarious faults occurred. The facilities used are extremely restricted ifnot minimal. Finally, the present invention uses a dynamic approach forfault assigning, in that part of the decision is delayed. Furthermore,the invention provides for signalling irrepairability.

FIG. 1A shows the operation modes of the architecture of FIG. 1. Inblock 50, control signal bistEnable controls the normal mode ofoperation: the BIST is idling, the various active items of the BIST aredisabled, and the BIST shell is transparent, notably blocks 28 and 30,so that only little influence is effected on the signal transfer. Thisstate may prevail for a long time, in particular after the manufacturingtest procedures have been terminated. Actuation of the bistEnable signalsteers the system to the Test Process of block 53. The test properalternates between two modes of operation 52, 54. In the mode StimGen52, Stimulus Generator 28 is in control, and the memory test is inprogress, such as according to a so-called March Test or anotherapplicable methodology. This test produces a sequence of address A anddata in DI pairs that are presented to memory 24, to eventually resultin a corresponding sequence of data out DO from memory 24. Moreover,Stimulus Generator 28 sends the address A and an associated expectedresponse ER to Response Evaluator 30. Generally although notrestrictively, the expected response ER is identical to an associateddata DI that had most recently been written into the memory locationassociated to this address. Note that a sequence of DI words for aseries of addresses may be mutually identical.

Now, data out DO received in block 30 from memory 24 are in the modeRespEval 54 compared with the appropriate data. In this respect, acomplete multi-address test sequence will be disclosed with respect toFIG. 2. Now, as long as the comparison does not find a discrepancybetween the Data Out and the expected response therefor, the halt signalfrom Response Evaluator 30 remains nonasserted, and the next test cycleproceeds. However, if the comparison does indeed find a discrepancy, thehalt signal from Response Evaluator 30 becomes asserted, and the nexttest cycle remains suspended. In block 54, the fault is evaluated aswill hereinafter be disclosed with reference to FIG. 3. This informationmay be used eventually outside chip 20, for then controlling a physicalrepair process, such as by fuse blowing. If the evaluation in block 54is finished, the halt signal is deasserted again, so that the testingcan continue in its prespecified manner. The present invention does notspecify a physical address sequence or the content of a test pattern, assuch is particular to the specific test applied. Eventually, the testwill be complete, and the system will exit from the test block 53.

Thereupon, the result from the evaluation as stored in the Table of FIG.5, will be read out, and communicated to an external analysis and repairdevice not shown herein. Communication may be performed via wire 34, viaone or more wires of bundle 36, or otherwise. The external device willnow know enough about the various faults detected to decide whether andwhat repair measures should be taken. By itself, the policy of suchmachine is not subject of the present invention, as such machine wouldbe able to operate in the same manner, given the memory bit faultsimmediately upon detection thereof. After the communication with theexternal device has been executed, the system of FIG. 1A may proceedagain to block 50.

FIG. 2 shows a finite state machine embodiment organized for executing a9N March Memory Test. For simplicity, only the various states have beenshown. After Initialization, words with content W0 are written in asequence of cycles, usually for all applicable addresses, each cyclepertaining to a single word location. Next, a sequence of locations isread in action R0, pertaining to all or to a fraction of those writtenearlier, to intentionally produce word W0 again, whilst in the sameaddressing operation cycle writing word W1 into the word location inquestion. These read/write cycles are then executed once more for athird data content, indicated as R1/W2. Next, these cycles are executedonce more for a fourth data content according to R2/W3, the latter beingread again immediately after writing without further address changing,as indicated by R3. Next, all words are read once more as indicated byR3A, for checking the actually stored content. This is the last step toarrive at 9 steps per address location. The diagram is completed with aReady state and with an Idle state. The 9N march test schedule is one ofseveral schemes in common use, and the present invention is not directedto such scheme in particular. In fact, the invention is likewiseapplicable if the addressing sequence were changed, if it were differentduring reading from writing, and if successive data words in a sequencewere mutually different.

FIG. 3 shows a response evaluator embodiment for use with the presentinvention. For simplicity, synchronization or other applicable controlof the circuitry has not been shown. At the top of the Figure, theexpected response pattern and actual response pattern in the currentembodiment both have a length of 240 bits, and for attaining a highspeed are bit by bit compared in parallel in block 60. The comparisonproduces for the embodiment a 240 bit current fault word that in block62 is bitwise ANDED with the “repaired bits information fault word” forthe actual address, that is a map of all faults that have been detectedand stored in the fault table of FIG. 5. If no faults had been found yetfor the current word, the comparison is a dummy operation. If theprevious fault word was non-zero, in block 66 the ANDED vector ischecked for an all-zero pattern. If yes, the halt signal remainsnon-asserted at “0”, and the testing continues. If the check does notdetect an all-zero pattern, a repair analysis is executed as will bedisclosed infra. It would be clear that the analysis result will only beoutputted in relatively infrequent situations. Note furthermore, thatnon-detecting a fault for a single address and pattern may still resultfrom a fault that remains undetected for the pattern in question, suchas a stuck-at fault.

The procedure according to the foregoing may be further extended asfollows. Because lossless compressed response signalization patterns mayoccur in long strings, the tester will then for a predetermined periodreceive only a single bit per clock cycle. Even if some faults will beactually detected, the overall run will take only little more time thanthe minimum. It is possible to estimate this extra time for variousfault patterns that are just repairable, and thereby estimate themaximally feasible test time. Now, memories of which the BIST proceduredid not complete within such estimated time length may be consideredunrepairable, so that the test in question may be aborted and thecircuit be scrapped. For simplicity, this extra check has not been shownin the diagrams. The choice of the maximum run length is a relevantparameter. Memory design should specify a range of maximally. repairablefault patterns, each pattern combined with the resulting signalizationbit length. The maximum value of this length, at a certain risk forbeing too pessimistic, may specify a somewhat lower value, such as 10%lower, and should apply for setting the above described maximumthreshold signalization length. Note that anyway, the length of theoverall signalization may not exceed the memory capacity of the externaltester.

A further feature is the defect-oriented address ordering. This featureis based on the fact that for March Testing the logic address orderingcan in principle be arbitrary. This degree of freedom may be used tochoose an address sequence in such manner that many successive addresseswill have the same fault pattern. The choosing may be done withoutknowing the actual faults. For example, because bitline faults willgenerally be the most likely ones, the address order of a March Test maybe chosen such that the test marches successively along the addressesthat share physical bit lines of the memory. Note that the physicaladdress within the memory array(s) need not be identical to the logicaladdress given by the address bits. In case of a failing bit line, thiswill then lead to communicating only a single full responsesignalization for that particular bit line failure. In particular, ithas been found that for certain memory technologies, column errors willhave the greatest probability.

FIG. 4 presents a repair analysis procedure in pseudocode form. Thereto,FIG. 5 is a block diagram of on-chip analysis hardware that does apartial repair analysis. Therein, item 70 is the memory array proper,that in this embodiment has sixteen rows of sixteen bits each. In commonpractice, it would be much larger, thus diminishing the relative amountof redundancy. For further enhancing clarity, various addressing andsynchronizing mechanisms, as well as the necessary data paths have beensuppressed in the arrangement of FIG. 5. The memory array has threeredundant columns 72 and two redundant rows 74, which numbers inpractice are often greater.

Next, the embodiment has a must repair table 76, that has r*(c+1)locations, each with a wordline address part 78 that can be addressed byassociation, and which address has four bits only in the embodiment. Thetable furthermore has a fault word part 80 that equals the array wordlength and can contain a fault map of the row that is pointed at by theaddress in its row address part.

The present embodiment uses a repair register 64 in FIG. 3 with a widththat equals the word length of the array to indicate which columns havebeen set for repair so far. Finally, for each array column there is aseparate counter facility 82, for counting the number of faults for thecolumn in question. This counter may be realized as a short register.Note that the number of bit faults in a column before deciding that aredundant column is necessary, equals the number of redundant rows,which usually is in the range 2-16, so necessitating at most a four-bitregister.

The on-chip processing does a partial repair analysis, based on the MustRepair strategy. The overall analysis strategy is based on the followingobservations. If c columns can be repaired, and a certain row i has morethan c faults, these faults cannot be all repaired by columns. Hence,row i must be repaired by a spare row.

Furthermore, if r rows can be repaired, and a certain column i has morethan r faults, these faults cannot be all repaired by rows. Hence,column i must be repaired by a spare column.

Now, the on-chip repair analysis operates as follows. First, the actualresponse pattern is bitwise compared to the expected response pattern toresult in a discrepancy pattern. The discrepancy pattern is compared toa repair register that indicates the faulty columns that had beendetected earlier. Only if a fault outside these columns is found, repairanalysis is undertaken. Then, first the wordline address column in thetable of FIG. 5 is scanned for the current wordline address. This may beeffected by a conventional associative search mechanism. If the rowaddress is not found and the table has empty space, then the actual wordline address and the actual fault word are stored in the table. If theword address cannot be found, but the table is full, then the memory isbeyond repair, and the test may be aborted. For simplicity, the abortmechanism has not been disclosed in detail.

However, if the word address is present in the table already, first thenew fault word is ORED with the existing table entry and stored. Next,the previous table entry is subtracted from the new table word and theresulting bits are used for incrementing the respectively associatedcolumn counters in counter facility 82. If the incrementing will lead toan overflow of one or more of the counters/registers, for the bitposition in question the fault bit in repair register 64 is set. Thismay be done expediently by ORING the counter carry bits and the existingcontent of the repair register.

Further to the above, a Table row that has a number of faults thatexceeds the number of replaceable columns can increment the number ofcolumns-to-be-repaired. If this number exceeds the number of redundantcolumns, the array is signalled as irrepairable, and the test procedureis aborted. Likewise, if the number of columns to be repaired in therepair register exceeds the number of redundant columns, the array issignalled as irrepairable, and the test procedure is aborted. If aparticular memory-containing chip has more arrays in parallel, varioussubstitution and/or higher level protective strategies could befollowed, but these are outside the ambit of the present invention. Thenumber of rows in the Table is determined as follows. A first number ofrow locations is used for storing faults whose rows could give rise toreplacing by a redundant row. In the embodiment this comes to twolocations. A second number of row locations is used for storing otherfaults that collectively could give rise to replacing by a redundantcolumn. The number of these faults cannot be higher than the product ofthe number of redundant columns and the number of redundant rows. Thetwo sets of row locations may form part of a single array. A reducedsolution can have only the second number of row locations, inasmuch asthis would cover a large fraction of all fault distributions. Forexample, if both numbers are equal to 16, part 80 would reduce from 272to only 256 locations, whilst using the same analysis program strategy.

In the above, the redundant rows and/or the redundant columns may betested in similar manner as the standard array rows and columns. Thiscould necessitate a greater width of table part 80 and also, a greateraddress span of table part 78. The procedure described applies similarlyto bit-organized arrays as to the word-organized array considered supra.It should be noted that interchanging rows and columns allowsmaintaining of the policy followed.

Hereabove, a few complications have not been treated. First, the testingis generally done on a word basis, inasmuch as the word is the unit thata computer uses for information handling. On the other hand, the memorymay be organized on the basis of rows, that may comprise a plurality ofwords, such as in the example wherein a row is 240 bits, that mayrepresent 15 words of 16 bits each. A bit-organized memory will thenhave a wordlength of only one bit. At the end of the test, the repairoperation will be organized on the basis of rows and columns.

What is claimed is:
 1. A built-in self-diagnostic (BISD) memory device,comprising: a two-dimension memory array subject to random bit faultswhich occur in manufacturing; a plurality of redundant memory rows andcolumns that can be substituted for various ones in the two-dimensionmemory array by an external repair facility; a test mode controller forinitiating a test mode in which the memory array is probed for saidrandom bit faults; a stimulus generator connected to outputmulti-address test sequences to the memory array during said test mode;a response evaluator connected to receive responses from the memoryduring said test mode, and able to halt the stimulus generator fromprogressing until an evaluation of said responses is ready; a faulttable for storing a plurality of evaluations of said responses, and forcommunicating them to said external repair facility; a repair registerdisposed in the fault table, and with a word length that equals the wordlength of the memory array, and for indicating which memory columns havebeen intermediately scheduled for repair by the response evaluator; aplurality of column counters disposed in the fault table, and each foraccumulating the number of memory bit faults detected in a respectivememory column; and a single integrated circuit semiconductor device inwhich all the above elements are disposed and packaged with a limitednumber of input/output pins.
 2. The device of claim 1, furthercomprising: a partial-repair analysis processor disposed in the responseevaluator and connected to the counter, and for determining if thenumber of bit faults in the two-dimension memory array exceeds thecapacity of the plurality of redundant memory rows and columns toeffectuate a repair by their optimal substitution, and able tocommunicate to said repair facility if the device is unrepairable. 3.The device of claim 2, wherein: the partial-repair analysis processor issuch that said communication to said repair facility that the device isunrepairable is issuable prior to the stimulus generator sequencingcompletely through the entire memory array.
 4. The device of claim 2,wherein: the partial-repair analysis processor determines in amust-repair process if the number of faults in a particular memory rowexceeds the number of redundant memory columns available, that suchmemory row must be repaired by substituting it with one of the redundantmemory rows.
 5. The device of claim 2, wherein: the partial-repairanalysis processor determines in a must-repair process if the number offaults in a particular memory column exceeds the number of redundantmemory rows available, that such memory column must be repaired bysubstituting it with one of the redundant memory columns.
 6. The deviceof claim 2, wherein: the repair register is used to indicate faultycolumns that had been detected in an earlier part of a test cycle, and adiscrepancy pattern is generated from a bitwise comparison of anexpected response to an actual response received from the memory array,and such discrepancy pattern is used to check if another faulty columnis being newly detected, and if so a repair analysis is launched by theresponse evaluator in which respective column counters are incrementedto determine if the device is unrepairable as indicated by a counteroverflow.